The present invention relates to formation of microelectronic devices, especially the formation of conductive pads.
Microelectronic devices generally comprise a thin slab of a semiconductor material, such as silicon or gallium arsenide, commonly called a die or a semiconductor chip. Semiconductor chips are commonly provided as individual, prepackaged units. In some unit designs, the semiconductor chip is mounted to a substrate or chip carrier, which is in turn mounted on a circuit panel, such as a printed circuit board.
The active circuitry is fabricated in a first face of the semiconductor chip (e.g., a front surface). To facilitate electrical connection to the active circuitry, the chip is provided with bond pads on the same face. The bond pads are generally made of a conductive metal, such as copper, or aluminum, around 0.5 μm thick. The bond pads could include a single layer or multiple layers of metal. The size of the bond pads will vary with the device type but will typically measure tens to hundreds of microns on a side.
Microelectronic devices are typically mounted in packages which include a dielectric element having a set of conductive elements thereon, such as terminals or other conductive pads. A packaged chip or in some cases a bare chip can be mounted to and electrically interconnected with the conductive pads of a circuit panel. Traditionally, the conductive pads on such dielectric element or circuit panel can be formed by rastering or photolithography. These processes can involve drawbacks. Laser formation of conductive pads by rastering can create pads with uneven surfaces, as each successive rastered segment partially overlaps the previous segment. Photolithography can be inefficient, particularly for small production quantities, pads, as it can be burdensome to design, test and correct a mask that is optimized for a particular application or system.
Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/O's.” These I/O's must be interconnected with the I/O's of other chips. The interconnections should be short and should have low impedance to minimize signal propagation delays. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines. For example, structures which provide numerous short, low-impedance interconnects between complex chips can increase the bandwidth of the search engine and reduce its power consumption.
Despite the advances that have been made or proposed in the fabrication of components with conductive pads further improvements can still be made.